EU-funded scientists successfully designed a digital-to-analogue (DAC) converter that demonstrates low distortion at high output frequencies. Pure waveforms are particularly important for new-generation wireless communications systems, cable TV or radio frequency equipment that demand high data rates.
Integrated circuit devices are not ideal components, and DACs are no exception. Device noise and non-linearity do not allow the frequency domain of a pure analogue signal to have all power concentrated at the desired frequency. System architects refer to the spurious-free dynamic range (SFDR) to measure the ratio between the fundamental signal and the largest noise or harmonic distortion component.
Looking to increase DAC performance and reliability, scientists within HSDAC (A 16-bit, 2 giga -sample-per-second, digital-to-analog converter with 85 dB SFDR at Fout=400MHz) performed significant work on reducing SFDR at high frequencies. The target was to achieve an SFDR value of 85 dB, which was 9 dB above the best available DAC as of 2014. Keeping SFDR low ensures that the transmitter will not send spurious signals into neighbouring frequency bands that transverse through the air or cables.
Scientists used diverse techniques such as parasitic extraction, Monte Carlo and corner analysis to design a low-power 16-bit dual-channel DAC. By optimising transistor sizes, minimising switching circuitry sizes and reducing time delays of segmented current sources, they obtained SFDR values lower than 78 dB at 240 MHz. After increasing the signal sampling rate, thus obtaining 1.1 GHz output frequency, and pruning the clock tree, the team achieved 85 dB SFDR with low output swing. A double data rate interface and a digital filter with quantisation properties were also designed that were able to support 95 dB SFDR.
In addition to the first DAC that employed double cascode current sources, the project team designed another one with output current stemming from a folded cascode. Different approaches were adopted to minimise cross-talk noise. Further layout iterations are necessary to exceed 85 dB SFDR in post-layout simulations.
Generating more accurate waveforms at high frequencies requires identifying and understanding the DAC error mechanisms. HSDAC made a pioneering contribution, with results being posted in numerous publications.
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