EU-funded scientists are developing new organic/inorganic materials that are excellent candidate elements for non-volatile memories. Being both electrically and optically addressed, they pave the way for converging electronic and photonic integrated circuits.
Non-volatile memory is a computer memory type that has the capability to
retain saved data even if the power is turned off. EU-funding of the
'Hybrid organic/inorganic memory elements for integration of electronic
and photonic circuitry' (
HYMEC)
project enabled further research into the fundamental information
storage mechanisms of nanostructured hybrid materials. These represent
potential interconnects of future hybrid electronic and photonic
circuitry.
Work is geared towards comprehending and controlling the resistance switching mechanisms of a system consisting of inorganic metal nanoparticles (NPs) embedded in conjugated organic material matrices. , Scientists also seek to significantly extend system functionality through optical and electrical addressing.
Project members have shown that charge storage occurs in metal NPs in an organic matrix, however, the NP charging state cannot be controlled electrically. As a result, devices are in the 'off' state. Furthermore, controlled device conditioning has enabled reversible forming and eliminating of conductive filaments. Full electrical writing/reading/erase cycles are therefore possible in non-volatile memory elements.
A novel method to integrate full optical addressing has been developed in hybrid devices, including writing and erasing, where electrical switching depends on filament formation. On the other side, functional non-volatile elements cannot be achieved in devices without filaments. These can be transiently switched to the 'on' state during illumination, however, they return to the 'off' stage when illumination is turned off.
HYMEC has shed further insight into the fundamental properties of NP / organic matrix system to further enhance non-volatile memory element function. Moreover, project members have provided reliable guidelines for device architecture optimisation and integration into memory arrays.
Future work includes cost-efficient fabrication routes such as printing and the miniaturisation of these memory elements at nanoscale lengths.